Currently the electronics fabrication industry is struggling with uniformly filling high aspect ratio (HAR) trenches with a spin-on material that has minimal shrinkage, i.e. <20%, at 1000° C. for 60 minutes under oxidative environments, produces high quality thermal oxide, results in a material with compressive stress, has equivalent electrical and mechanical properties as thermal oxide, and is capable of planarizing a variety of features. All of these properties must be met for consideration in front end of the line (FEOL) processes. The current material, polysilazane, works well, but it appears that it exhibits compositional gradients, suffers from significant out-gassing, has significant storage stability issues, and is expensive.
Relevant prior art in this area includes: U.S. Pat. No. 7,270,886; U.S. Pat. No. 7,192,891; U.S. Pat. No. 7,179,537; U.S. Pat. No. 7,053,005; U.S. Pat. No. 7,015,144; U.S. Pat. No. 6,706,646; U.S. Pat. No. 6,635,586; U.S. Pat. No. 6,489,252; U.S. Pat. No. 6,479,405; U.S. Pat. No. 6,432,843; U.S. Pat. No. 7,037,840; U.S. Pat. No. 6,869,860; EP1 768 175; EP1 608 012; EP1 278 238; EP1 380 612; EP1 002 824; EP1 500 685; U.S. Pat. No. 7,153,783; U.S. Pat. No. 6,167,172; US2006/0051929(A1); US2005/0239264(A1); and U.S. Pat. No. 7,223,802.